// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  dvpp0_cfg_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  Huawei
// Version       :  1.0
// Date          :  2017/11/13
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/03/19 15:36:22 Create file
// ******************************************************************************

#ifndef __DVPP0_CFG_REG_OFFSET_FIELD_H__
#define __DVPP0_CFG_REG_OFFSET_FIELD_H__

#define DVPP0_CFG_ICG_EN_SMMU0_TRANS_LEN    1
#define DVPP0_CFG_ICG_EN_SMMU0_TRANS_OFFSET 0

#define DVPP0_CFG_ICG_DIS_SMMU0_TRANS_LEN    1
#define DVPP0_CFG_ICG_DIS_SMMU0_TRANS_OFFSET 0

#define DVPP0_CFG_ICG_EN_PNGD_LEN    6
#define DVPP0_CFG_ICG_EN_PNGD_OFFSET 0

#define DVPP0_CFG_ICG_DIS_PNGD_LEN    6
#define DVPP0_CFG_ICG_DIS_PNGD_OFFSET 0

#define DVPP0_CFG_ICG_EN_VPC_LEN    4
#define DVPP0_CFG_ICG_EN_VPC_OFFSET 0

#define DVPP0_CFG_ICG_DIS_VPC_LEN    4
#define DVPP0_CFG_ICG_DIS_VPC_OFFSET 0

#define DVPP0_CFG_ICG_EN_VENC_LEN    1
#define DVPP0_CFG_ICG_EN_VENC_OFFSET 0

#define DVPP0_CFG_ICG_DIS_VENC_LEN    1
#define DVPP0_CFG_ICG_DIS_VENC_OFFSET 0

#define DVPP0_CFG_ICG_EN_SMMU1_TRANS_LEN    1
#define DVPP0_CFG_ICG_EN_SMMU1_TRANS_OFFSET 0

#define DVPP0_CFG_ICG_DIS_SMMU1_TRANS_LEN    1
#define DVPP0_CFG_ICG_DIS_SMMU1_TRANS_OFFSET 0

#define DVPP0_CFG_ICG_EN_FTE_LEN    1
#define DVPP0_CFG_ICG_EN_FTE_OFFSET 0

#define DVPP0_CFG_ICG_DIS_FTE_LEN    1
#define DVPP0_CFG_ICG_DIS_FTE_OFFSET 0

#define DVPP0_CFG_ICG_EN_VDEC_LEN    2
#define DVPP0_CFG_ICG_EN_VDEC_OFFSET 0

#define DVPP0_CFG_ICG_DIS_VDEC_LEN    2
#define DVPP0_CFG_ICG_DIS_VDEC_OFFSET 0

#define DVPP0_CFG_ICG_EN_JPG_LEN    1
#define DVPP0_CFG_ICG_EN_JPG_OFFSET 0

#define DVPP0_CFG_ICG_DIS_JPG_LEN    1
#define DVPP0_CFG_ICG_DIS_JPG_OFFSET 0

#define DVPP0_CFG_ICG_EN_I2C_LEN    2
#define DVPP0_CFG_ICG_EN_I2C_OFFSET 0

#define DVPP0_CFG_ICG_DIS_I2C_LEN    2
#define DVPP0_CFG_ICG_DIS_I2C_OFFSET 0

#define DVPP0_CFG_ICG_EN_UART_LEN    1
#define DVPP0_CFG_ICG_EN_UART_OFFSET 0

#define DVPP0_CFG_ICG_DIS_UART_LEN    1
#define DVPP0_CFG_ICG_DIS_UART_OFFSET 0

#define DVPP0_CFG_ICG_EN_SPI_LEN    3
#define DVPP0_CFG_ICG_EN_SPI_OFFSET 0

#define DVPP0_CFG_ICG_DIS_SPI_LEN    3
#define DVPP0_CFG_ICG_DIS_SPI_OFFSET 0

#define DVPP0_CFG_ICG_EN_GPIO_LEN    2
#define DVPP0_CFG_ICG_EN_GPIO_OFFSET 0

#define DVPP0_CFG_ICG_DIS_GPIO_LEN    2
#define DVPP0_CFG_ICG_DIS_GPIO_OFFSET 0

#define DVPP0_CFG_ICG_EN_MDIO_LEN    1
#define DVPP0_CFG_ICG_EN_MDIO_OFFSET 0

#define DVPP0_CFG_ICG_DIS_MDIO_LEN    1
#define DVPP0_CFG_ICG_DIS_MDIO_OFFSET 0

#define DVPP0_CFG_ICG_EN_DDR0_LEN    4
#define DVPP0_CFG_ICG_EN_DDR0_OFFSET 0

#define DVPP0_CFG_ICG_DIS_DDR0_LEN    4
#define DVPP0_CFG_ICG_DIS_DDR0_OFFSET 0

#define DVPP0_CFG_ICG_EN_HHA0_LEN    1
#define DVPP0_CFG_ICG_EN_HHA0_OFFSET 0

#define DVPP0_CFG_ICG_DIS_HHA0_LEN    1
#define DVPP0_CFG_ICG_DIS_HHA0_OFFSET 0

#define DVPP0_CFG_ICG_EN_MN0_LEN    1
#define DVPP0_CFG_ICG_EN_MN0_OFFSET 0

#define DVPP0_CFG_ICG_DIS_MN0_LEN    1
#define DVPP0_CFG_ICG_DIS_MN0_OFFSET 0

#define DVPP0_CFG_ICG_EN_EXMBIST0_CFG_LEN     1
#define DVPP0_CFG_ICG_EN_EXMBIST0_CFG_OFFSET  1
#define DVPP0_CFG_ICG_EN_EXMBIST0_ACLK_LEN    1
#define DVPP0_CFG_ICG_EN_EXMBIST0_ACLK_OFFSET 0

#define DVPP0_CFG_ICG_DIS_EXMBIST0_CFG_LEN     1
#define DVPP0_CFG_ICG_DIS_EXMBIST0_CFG_OFFSET  1
#define DVPP0_CFG_ICG_DIS_EXMBIST0_ACLK_LEN    1
#define DVPP0_CFG_ICG_DIS_EXMBIST0_ACLK_OFFSET 0

#define DVPP0_CFG_ICG_EN_DUM_APB0_LEN    1
#define DVPP0_CFG_ICG_EN_DUM_APB0_OFFSET 2
#define DVPP0_CFG_ICG_EN_P2P_M0_LEN      1
#define DVPP0_CFG_ICG_EN_P2P_M0_OFFSET   1

#define DVPP0_CFG_ICG_DIS_DUM_APB0_LEN    1
#define DVPP0_CFG_ICG_DIS_DUM_APB0_OFFSET 2
#define DVPP0_CFG_ICG_DIS_P2P_M0_LEN      1
#define DVPP0_CFG_ICG_DIS_P2P_M0_OFFSET   1

#define DVPP0_CFG_ICG_EN_L2BUFF0_LEN    1
#define DVPP0_CFG_ICG_EN_L2BUFF0_OFFSET 0

#define DVPP0_CFG_ICG_DIS_L2BUFF0_LEN    1
#define DVPP0_CFG_ICG_DIS_L2BUFF0_OFFSET 0

#define DVPP0_CFG_SRST_REQ_PNGD_LEN    6
#define DVPP0_CFG_SRST_REQ_PNGD_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_PNGD_LEN    6
#define DVPP0_CFG_SRST_DREQ_PNGD_OFFSET 0

#define DVPP0_CFG_SRST_REQ_VPC_APB_LEN    4
#define DVPP0_CFG_SRST_REQ_VPC_APB_OFFSET 4
#define DVPP0_CFG_SRST_REQ_VPC_LEN        4
#define DVPP0_CFG_SRST_REQ_VPC_OFFSET     0

#define DVPP0_CFG_SRST_DREQ_VPC_APB_LEN    4
#define DVPP0_CFG_SRST_DREQ_VPC_APB_OFFSET 4
#define DVPP0_CFG_SRST_DREQ_VPC_LEN        4
#define DVPP0_CFG_SRST_DREQ_VPC_OFFSET     0

#define DVPP0_CFG_SRST_REQ_VENC_APB_LEN    1
#define DVPP0_CFG_SRST_REQ_VENC_APB_OFFSET 2
#define DVPP0_CFG_SRST_REQ_VENC_AXI_LEN    1
#define DVPP0_CFG_SRST_REQ_VENC_AXI_OFFSET 1
#define DVPP0_CFG_SRST_REQ_VENC_LEN        1
#define DVPP0_CFG_SRST_REQ_VENC_OFFSET     0

#define DVPP0_CFG_SRST_DREQ_VENC_APB_LEN    1
#define DVPP0_CFG_SRST_DREQ_VENC_APB_OFFSET 2
#define DVPP0_CFG_SRST_DREQ_VENC_AXI_LEN    1
#define DVPP0_CFG_SRST_DREQ_VENC_AXI_OFFSET 1
#define DVPP0_CFG_SRST_DREQ_VENC_LEN        1
#define DVPP0_CFG_SRST_DREQ_VENC_OFFSET     0

#define DVPP0_CFG_SRST_REQ_FTE_LEN    1
#define DVPP0_CFG_SRST_REQ_FTE_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_FTE_LEN    1
#define DVPP0_CFG_SRST_DREQ_FTE_OFFSET 0

#define DVPP0_CFG_SRST_REQ_VDEC_LEN    2
#define DVPP0_CFG_SRST_REQ_VDEC_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_VDEC_LEN    2
#define DVPP0_CFG_SRST_DREQ_VDEC_OFFSET 0

#define DVPP0_CFG_SRST_REQ_JPG_APB_LEN    1
#define DVPP0_CFG_SRST_REQ_JPG_APB_OFFSET 2
#define DVPP0_CFG_SRST_REQ_JPG_AXI_LEN    1
#define DVPP0_CFG_SRST_REQ_JPG_AXI_OFFSET 1
#define DVPP0_CFG_SRST_REQ_JPG_LEN        1
#define DVPP0_CFG_SRST_REQ_JPG_OFFSET     0

#define DVPP0_CFG_SRST_DREQ_JPG_APB_LEN    1
#define DVPP0_CFG_SRST_DREQ_JPG_APB_OFFSET 2
#define DVPP0_CFG_SRST_DREQ_JPG_AXI_LEN    1
#define DVPP0_CFG_SRST_DREQ_JPG_AXI_OFFSET 1
#define DVPP0_CFG_SRST_DREQ_JPG_LEN        1
#define DVPP0_CFG_SRST_DREQ_JPG_OFFSET     0

#define DVPP0_CFG_SRST_REQ_I2C_LEN    2
#define DVPP0_CFG_SRST_REQ_I2C_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_I2C_LEN    2
#define DVPP0_CFG_SRST_DREQ_I2C_OFFSET 0

#define DVPP0_CFG_SRST_REQ_UART_LEN    1
#define DVPP0_CFG_SRST_REQ_UART_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_UART_LEN    1
#define DVPP0_CFG_SRST_DREQ_UART_OFFSET 0

#define DVPP0_CFG_SRST_REQ_SPI_LEN    3
#define DVPP0_CFG_SRST_REQ_SPI_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_SPI_LEN    3
#define DVPP0_CFG_SRST_DREQ_SPI_OFFSET 0

#define DVPP0_CFG_SRST_REQ_GPIO_LEN    2
#define DVPP0_CFG_SRST_REQ_GPIO_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_GPIO_LEN    2
#define DVPP0_CFG_SRST_DREQ_GPIO_OFFSET 0

#define DVPP0_CFG_SRST_REQ_MDIO_LEN    1
#define DVPP0_CFG_SRST_REQ_MDIO_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_MDIO_LEN    1
#define DVPP0_CFG_SRST_DREQ_MDIO_OFFSET 0

#define DVPP0_CFG_SRST_REQ_DDR0_LEN    4
#define DVPP0_CFG_SRST_REQ_DDR0_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_DDR0_LEN    4
#define DVPP0_CFG_SRST_DREQ_DDR0_OFFSET 0

#define DVPP0_CFG_SRST_REQ_HHA0_LEN    1
#define DVPP0_CFG_SRST_REQ_HHA0_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_HHA0_LEN    1
#define DVPP0_CFG_SRST_DREQ_HHA0_OFFSET 0

#define DVPP0_CFG_SRST_REQ_MN0_LEN    1
#define DVPP0_CFG_SRST_REQ_MN0_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_MN0_LEN    1
#define DVPP0_CFG_SRST_DREQ_MN0_OFFSET 0

#define DVPP0_CFG_SRST_REQ_EXMBIST0_ARESET_LEN    1
#define DVPP0_CFG_SRST_REQ_EXMBIST0_ARESET_OFFSET 1
#define DVPP0_CFG_SRST_REQ_EXMBIST0_LEN           1
#define DVPP0_CFG_SRST_REQ_EXMBIST0_OFFSET        0

#define DVPP0_CFG_SRST_DREQ_EXMBIST0_ARESET_LEN    1
#define DVPP0_CFG_SRST_DREQ_EXMBIST0_ARESET_OFFSET 1
#define DVPP0_CFG_SRST_DREQ_EXMBIST0_LEN           1
#define DVPP0_CFG_SRST_DREQ_EXMBIST0_OFFSET        0

#define DVPP0_CFG_SRST_REQ_DUM0_LEN      1
#define DVPP0_CFG_SRST_REQ_DUM0_OFFSET   2
#define DVPP0_CFG_SRST_REQ_P2P_M0_LEN    1
#define DVPP0_CFG_SRST_REQ_P2P_M0_OFFSET 1

#define DVPP0_CFG_SRST_DREQ_DUM0_LEN      1
#define DVPP0_CFG_SRST_DREQ_DUM0_OFFSET   2
#define DVPP0_CFG_SRST_DREQ_P2P_M0_LEN    1
#define DVPP0_CFG_SRST_DREQ_P2P_M0_OFFSET 1

#define DVPP0_CFG_SRST_REQ_L2BUFF0_LEN    1
#define DVPP0_CFG_SRST_REQ_L2BUFF0_OFFSET 0

#define DVPP0_CFG_SRST_DREQ_L2BUFF0_LEN    1
#define DVPP0_CFG_SRST_DREQ_L2BUFF0_OFFSET 0

#define DVPP0_CFG_AO_RESET_CTRL_DDR0_LEN    4
#define DVPP0_CFG_AO_RESET_CTRL_DDR0_OFFSET 0

#define DVPP0_CFG_BYP_MODE_DDRC3_LEN    1
#define DVPP0_CFG_BYP_MODE_DDRC3_OFFSET 3
#define DVPP0_CFG_BYP_MODE_DDRC2_LEN    1
#define DVPP0_CFG_BYP_MODE_DDRC2_OFFSET 2
#define DVPP0_CFG_BYP_MODE_DDRC1_LEN    1
#define DVPP0_CFG_BYP_MODE_DDRC1_OFFSET 1
#define DVPP0_CFG_BYP_MODE_DDRC0_LEN    1
#define DVPP0_CFG_BYP_MODE_DDRC0_OFFSET 0

#define DVPP0_CFG_SPI2_CS_POLARITY_LEN    4
#define DVPP0_CFG_SPI2_CS_POLARITY_OFFSET 8
#define DVPP0_CFG_SPI1_CS_POLARITY_LEN    4
#define DVPP0_CFG_SPI1_CS_POLARITY_OFFSET 4
#define DVPP0_CFG_SPI0_CS_POLARITY_LEN    4
#define DVPP0_CFG_SPI0_CS_POLARITY_OFFSET 0

#define DVPP0_CFG_I2C0_SDA_CFG_SET_LEN        1
#define DVPP0_CFG_I2C0_SDA_CFG_SET_OFFSET     11
#define DVPP0_CFG_I2C0_DAT_OE_CFG_SET_LEN     1
#define DVPP0_CFG_I2C0_DAT_OE_CFG_SET_OFFSET  10
#define DVPP0_CFG_I2C0_DAT_MUX_SEL_SET_LEN    1
#define DVPP0_CFG_I2C0_DAT_MUX_SEL_SET_OFFSET 9
#define DVPP0_CFG_I2C0_SCL_CFG_SET_LEN        1
#define DVPP0_CFG_I2C0_SCL_CFG_SET_OFFSET     8
#define DVPP0_CFG_I2C0_CLK_OE_CFG_SET_LEN     1
#define DVPP0_CFG_I2C0_CLK_OE_CFG_SET_OFFSET  7
#define DVPP0_CFG_I2C0_CLK_MUX_SEL_SET_LEN    1
#define DVPP0_CFG_I2C0_CLK_MUX_SEL_SET_OFFSET 6
#define DVPP0_CFG_I2C1_SDA_CFG_SET_LEN        1
#define DVPP0_CFG_I2C1_SDA_CFG_SET_OFFSET     5
#define DVPP0_CFG_I2C1_DAT_OE_CFG_SET_LEN     1
#define DVPP0_CFG_I2C1_DAT_OE_CFG_SET_OFFSET  4
#define DVPP0_CFG_I2C1_DAT_MUX_SEL_SET_LEN    1
#define DVPP0_CFG_I2C1_DAT_MUX_SEL_SET_OFFSET 3
#define DVPP0_CFG_I2C1_SCL_CFG_SET_LEN        1
#define DVPP0_CFG_I2C1_SCL_CFG_SET_OFFSET     2
#define DVPP0_CFG_I2C1_CLK_OE_CFG_SET_LEN     1
#define DVPP0_CFG_I2C1_CLK_OE_CFG_SET_OFFSET  1
#define DVPP0_CFG_I2C1_CLK_MUX_SEL_SET_LEN    1
#define DVPP0_CFG_I2C1_CLK_MUX_SEL_SET_OFFSET 0

#define DVPP0_CFG_I2C0_SDA_CFG_CLR_LEN        1
#define DVPP0_CFG_I2C0_SDA_CFG_CLR_OFFSET     11
#define DVPP0_CFG_I2C0_DAT_OE_CFG_CLR_LEN     1
#define DVPP0_CFG_I2C0_DAT_OE_CFG_CLR_OFFSET  10
#define DVPP0_CFG_I2C0_DAT_MUX_SEL_CLR_LEN    1
#define DVPP0_CFG_I2C0_DAT_MUX_SEL_CLR_OFFSET 9
#define DVPP0_CFG_I2C0_SCL_CFG_CLR_LEN        1
#define DVPP0_CFG_I2C0_SCL_CFG_CLR_OFFSET     8
#define DVPP0_CFG_I2C0_CLK_OE_CFG_CLR_LEN     1
#define DVPP0_CFG_I2C0_CLK_OE_CFG_CLR_OFFSET  7
#define DVPP0_CFG_I2C0_CLK_MUX_SEL_CLR_LEN    1
#define DVPP0_CFG_I2C0_CLK_MUX_SEL_CLR_OFFSET 6
#define DVPP0_CFG_I2C1_SDA_CFG_CLR_LEN        1
#define DVPP0_CFG_I2C1_SDA_CFG_CLR_OFFSET     5
#define DVPP0_CFG_I2C1_DAT_OE_CFG_CLR_LEN     1
#define DVPP0_CFG_I2C1_DAT_OE_CFG_CLR_OFFSET  4
#define DVPP0_CFG_I2C1_DAT_MUX_SEL_CLR_LEN    1
#define DVPP0_CFG_I2C1_DAT_MUX_SEL_CLR_OFFSET 3
#define DVPP0_CFG_I2C1_SCL_CFG_CLR_LEN        1
#define DVPP0_CFG_I2C1_SCL_CFG_CLR_OFFSET     2
#define DVPP0_CFG_I2C1_CLK_OE_CFG_CLR_LEN     1
#define DVPP0_CFG_I2C1_CLK_OE_CFG_CLR_OFFSET  1
#define DVPP0_CFG_I2C1_CLK_MUX_SEL_CLR_LEN    1
#define DVPP0_CFG_I2C1_CLK_MUX_SEL_CLR_OFFSET 0

#define DVPP0_CFG_MDIO0_INTF_MODE_PORT4_LEN    1
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT4_OFFSET 4
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT3_LEN    1
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT3_OFFSET 3
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT2_LEN    1
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT2_OFFSET 2
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT1_LEN    1
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT1_OFFSET 1
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT0_LEN    1
#define DVPP0_CFG_MDIO0_INTF_MODE_PORT0_OFFSET 0

#define DVPP0_CFG_ERRRSP_DISABLE0_LEN    1
#define DVPP0_CFG_ERRRSP_DISABLE0_OFFSET 0

#define DVPP0_CFG_ERRRSP_DISABLE1_LEN    1
#define DVPP0_CFG_ERRRSP_DISABLE1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD0_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD0_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD0_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD0_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD1_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD1_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD1_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD1_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_ARQOS_PNGD0_LEN    4
#define DVPP0_CFG_SC_ARQOS_PNGD0_OFFSET 4
#define DVPP0_CFG_SC_AWQOS_PNGD0_LEN    4
#define DVPP0_CFG_SC_AWQOS_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_ARQOS_PNGD1_LEN    4
#define DVPP0_CFG_SC_ARQOS_PNGD1_OFFSET 4
#define DVPP0_CFG_SC_AWQOS_PNGD1_LEN    4
#define DVPP0_CFG_SC_AWQOS_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_ARQOS_PNGD2_LEN    4
#define DVPP0_CFG_SC_ARQOS_PNGD2_OFFSET 4
#define DVPP0_CFG_SC_AWQOS_PNGD2_LEN    4
#define DVPP0_CFG_SC_AWQOS_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_ARQOS_PNGD3_LEN    4
#define DVPP0_CFG_SC_ARQOS_PNGD3_OFFSET 4
#define DVPP0_CFG_SC_AWQOS_PNGD3_LEN    4
#define DVPP0_CFG_SC_AWQOS_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_ARQOS_PNGD4_LEN    4
#define DVPP0_CFG_SC_ARQOS_PNGD4_OFFSET 4
#define DVPP0_CFG_SC_AWQOS_PNGD4_LEN    4
#define DVPP0_CFG_SC_AWQOS_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_ARQOS_PNGD5_LEN    4
#define DVPP0_CFG_SC_ARQOS_PNGD5_OFFSET 4
#define DVPP0_CFG_SC_AWQOS_PNGD5_LEN    4
#define DVPP0_CFG_SC_AWQOS_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD2_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD2_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD2_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD2_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD3_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD3_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD3_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD3_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD4_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD4_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD4_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD4_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD5_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD5_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_PNGD5_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD5_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_PNGD5_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_VENC_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_VENC_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_VENC_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_VENC_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_VENC_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_VDEC0_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_VDEC0_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_VDEC0_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_VDEC0_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWADDR_EXT_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_AWADDR_EXT_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARADDR_EXT_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_ARADDR_EXT_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_L_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_L_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_M_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_M_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWUSER_H_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_AWUSER_H_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_L_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_L_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_M_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_M_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_ARUSER_H_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_ARUSER_H_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_SHIM_CTRL_VDEC1_LEN    32
#define DVPP0_CFG_SC_CFG_SHIM_CTRL_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_CFG_AWCACHE_VDEC1_LEN    4
#define DVPP0_CFG_SC_CFG_AWCACHE_VDEC1_OFFSET 4
#define DVPP0_CFG_SC_CFG_ARCACHE_VDEC1_LEN    4
#define DVPP0_CFG_SC_CFG_ARCACHE_VDEC1_OFFSET 0

#define DVPP0_CFG_SC_SOFT_REQ_PNGD0_LEN    1
#define DVPP0_CFG_SC_SOFT_REQ_PNGD0_OFFSET 0

#define DVPP0_CFG_SC_SOFT_REQ_PNGD1_LEN    1
#define DVPP0_CFG_SC_SOFT_REQ_PNGD1_OFFSET 0

#define DVPP0_CFG_SC_SOFT_REQ_PNGD2_LEN    1
#define DVPP0_CFG_SC_SOFT_REQ_PNGD2_OFFSET 0

#define DVPP0_CFG_SC_SOFT_REQ_PNGD3_LEN    1
#define DVPP0_CFG_SC_SOFT_REQ_PNGD3_OFFSET 0

#define DVPP0_CFG_SC_SOFT_REQ_PNGD4_LEN    1
#define DVPP0_CFG_SC_SOFT_REQ_PNGD4_OFFSET 0

#define DVPP0_CFG_SC_SOFT_REQ_PNGD5_LEN    1
#define DVPP0_CFG_SC_SOFT_REQ_PNGD5_OFFSET 0

#define DVPP0_CFG_MEM_POWER_MODE_SMMU0_LEN    6
#define DVPP0_CFG_MEM_POWER_MODE_SMMU0_OFFSET 7
#define DVPP0_CFG_SP_RAM_TMOD_SMMU0_LEN       7
#define DVPP0_CFG_SP_RAM_TMOD_SMMU0_OFFSET    0

#define DVPP0_CFG_MEM_POWER_MODE_SMMU1_LEN    6
#define DVPP0_CFG_MEM_POWER_MODE_SMMU1_OFFSET 7
#define DVPP0_CFG_SP_RAM_TMOD_SMMU1_LEN       7
#define DVPP0_CFG_SP_RAM_TMOD_SMMU1_OFFSET    0

#define DVPP0_CFG_SC_BYP_EN_VDEC1_LEN    1
#define DVPP0_CFG_SC_BYP_EN_VDEC1_OFFSET 1
#define DVPP0_CFG_SC_BYP_EN_VDEC0_LEN    1
#define DVPP0_CFG_SC_BYP_EN_VDEC0_OFFSET 0

#define DVPP0_CFG_SC_UART_SEL_LEN    3
#define DVPP0_CFG_SC_UART_SEL_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VDEC0_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VDEC0_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VDEC0_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VDEC0_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VDEC1_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VDEC1_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VDEC1_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VDEC1_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC0_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC0_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC0_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC0_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC0_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC1_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC1_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC1_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC1_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC1_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC2_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC2_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC2_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC2_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC2_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC3_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC3_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VPC3_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VPC3_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VPC3_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_JPEG_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_JPEG_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_JPEG_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_JPEG_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_JPEG_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VENC_CFG_AR_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AR_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VENC_CFG_AR_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_VALUE1_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_VALUE1_OFFSET 16
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_VALUE0_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_VALUE0_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_NUM1_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_NUM1_OFFSET 16
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_NUM0_LEN    16
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_NUM0_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_WINDOW_LEN    28
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_WINDOW_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_MODE_LEN    4
#define DVPP0_CFG_SC_VENC_CFG_AW_CMD_TIMEOUT_MODE_OFFSET 0

#define DVPP0_CFG_SC_VENC_CFG_AW_QOS_CTL_BP_EN_LEN    1
#define DVPP0_CFG_SC_VENC_CFG_AW_QOS_CTL_BP_EN_OFFSET 0

#define DVPP0_CFG_SC_CFG_QOS_BP_MASK_LEN    32
#define DVPP0_CFG_SC_CFG_QOS_BP_MASK_OFFSET 0

#define DVPP0_CFG_SC_CFG_QOS_BP_EN_LEN      1
#define DVPP0_CFG_SC_CFG_QOS_BP_EN_OFFSET   3
#define DVPP0_CFG_SC_CFG_QOS_BP_MODE_LEN    3
#define DVPP0_CFG_SC_CFG_QOS_BP_MODE_OFFSET 0

#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC0_LEN    1
#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC0_OFFSET 0

#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC1_LEN    1
#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC1_OFFSET 0

#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC2_LEN    1
#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC2_OFFSET 0

#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC3_LEN    1
#define DVPP0_CFG_SC_CMDLST_WR_MASK_VPC3_OFFSET 0

#define DVPP0_CFG_RST_STATE_DDR3_LEN    1
#define DVPP0_CFG_RST_STATE_DDR3_OFFSET 3
#define DVPP0_CFG_RST_STATE_DDR2_LEN    1
#define DVPP0_CFG_RST_STATE_DDR2_OFFSET 2
#define DVPP0_CFG_RST_STATE_DDR1_LEN    1
#define DVPP0_CFG_RST_STATE_DDR1_OFFSET 1
#define DVPP0_CFG_RST_STATE_DDR0_LEN    1
#define DVPP0_CFG_RST_STATE_DDR0_OFFSET 0

#define DVPP0_CFG_ICG_ST_SMMU0_TRANS_LEN    1
#define DVPP0_CFG_ICG_ST_SMMU0_TRANS_OFFSET 0

#define DVPP0_CFG_ICG_ST_PNGD_LEN    6
#define DVPP0_CFG_ICG_ST_PNGD_OFFSET 0

#define DVPP0_CFG_ICG_ST_VPC_LEN    4
#define DVPP0_CFG_ICG_ST_VPC_OFFSET 0

#define DVPP0_CFG_ICG_ST_VENC_LEN    1
#define DVPP0_CFG_ICG_ST_VENC_OFFSET 0

#define DVPP0_CFG_ICG_ST_SMMU1_TRANS_LEN    1
#define DVPP0_CFG_ICG_ST_SMMU1_TRANS_OFFSET 0

#define DVPP0_CFG_ICG_ST_FTE_LEN    1
#define DVPP0_CFG_ICG_ST_FTE_OFFSET 0

#define DVPP0_CFG_ICG_ST_VDEC_LEN    2
#define DVPP0_CFG_ICG_ST_VDEC_OFFSET 0

#define DVPP0_CFG_ICG_ST_JPG_LEN    1
#define DVPP0_CFG_ICG_ST_JPG_OFFSET 0

#define DVPP0_CFG_ICG_ST_I2C_LEN    2
#define DVPP0_CFG_ICG_ST_I2C_OFFSET 0

#define DVPP0_CFG_ICG_ST_UART_LEN    1
#define DVPP0_CFG_ICG_ST_UART_OFFSET 0

#define DVPP0_CFG_ICG_ST_SPI_LEN    3
#define DVPP0_CFG_ICG_ST_SPI_OFFSET 0

#define DVPP0_CFG_ICG_ST_GPIO_LEN    2
#define DVPP0_CFG_ICG_ST_GPIO_OFFSET 0

#define DVPP0_CFG_ICG_ST_MDIO_LEN    1
#define DVPP0_CFG_ICG_ST_MDIO_OFFSET 0

#define DVPP0_CFG_ICG_ST_DDR0_LEN    4
#define DVPP0_CFG_ICG_ST_DDR0_OFFSET 0

#define DVPP0_CFG_ICG_ST_HHA0_LEN    1
#define DVPP0_CFG_ICG_ST_HHA0_OFFSET 0

#define DVPP0_CFG_ICG_ST_MN0_LEN    1
#define DVPP0_CFG_ICG_ST_MN0_OFFSET 0

#define DVPP0_CFG_ICG_ST_EXMBIST0_CFG_LEN     1
#define DVPP0_CFG_ICG_ST_EXMBIST0_CFG_OFFSET  1
#define DVPP0_CFG_ICG_ST_EXMBIST0_ACLK_LEN    1
#define DVPP0_CFG_ICG_ST_EXMBIST0_ACLK_OFFSET 0

#define DVPP0_CFG_ICG_ST_DUM_APB0_LEN    1
#define DVPP0_CFG_ICG_ST_DUM_APB0_OFFSET 2
#define DVPP0_CFG_ICG_ST_P2P_M0_LEN      1
#define DVPP0_CFG_ICG_ST_P2P_M0_OFFSET   1

#define DVPP0_CFG_ICG_ST_L2BUFF0_LEN    1
#define DVPP0_CFG_ICG_ST_L2BUFF0_OFFSET 0

#define DVPP0_CFG_SRST_ST_PNGD_LEN    6
#define DVPP0_CFG_SRST_ST_PNGD_OFFSET 0

#define DVPP0_CFG_SRST_ST_VPC_APB_LEN    4
#define DVPP0_CFG_SRST_ST_VPC_APB_OFFSET 4
#define DVPP0_CFG_SRST_ST_VPC_LEN        4
#define DVPP0_CFG_SRST_ST_VPC_OFFSET     0

#define DVPP0_CFG_SRST_ST_VENC_APB_LEN    1
#define DVPP0_CFG_SRST_ST_VENC_APB_OFFSET 2
#define DVPP0_CFG_SRST_ST_VENC_AXI_LEN    1
#define DVPP0_CFG_SRST_ST_VENC_AXI_OFFSET 1
#define DVPP0_CFG_SRST_ST_VENC_LEN        1
#define DVPP0_CFG_SRST_ST_VENC_OFFSET     0

#define DVPP0_CFG_SRST_ST_FTE_LEN    1
#define DVPP0_CFG_SRST_ST_FTE_OFFSET 0

#define DVPP0_CFG_SRST_ST_VDEC_LEN    2
#define DVPP0_CFG_SRST_ST_VDEC_OFFSET 0

#define DVPP0_CFG_SRST_ST_JPG_APB_LEN    1
#define DVPP0_CFG_SRST_ST_JPG_APB_OFFSET 2
#define DVPP0_CFG_SRST_ST_JPG_AXI_LEN    1
#define DVPP0_CFG_SRST_ST_JPG_AXI_OFFSET 1
#define DVPP0_CFG_SRST_ST_JPG_LEN        1
#define DVPP0_CFG_SRST_ST_JPG_OFFSET     0

#define DVPP0_CFG_SRST_ST_I2C_LEN    2
#define DVPP0_CFG_SRST_ST_I2C_OFFSET 0

#define DVPP0_CFG_SRST_ST_UART_LEN    1
#define DVPP0_CFG_SRST_ST_UART_OFFSET 0

#define DVPP0_CFG_SRST_ST_SPI_LEN    3
#define DVPP0_CFG_SRST_ST_SPI_OFFSET 0

#define DVPP0_CFG_SRST_ST_GPIO_LEN    2
#define DVPP0_CFG_SRST_ST_GPIO_OFFSET 0

#define DVPP0_CFG_SRST_ST_MDIO_LEN    1
#define DVPP0_CFG_SRST_ST_MDIO_OFFSET 0

#define DVPP0_CFG_SRST_ST_DDR0_LEN    4
#define DVPP0_CFG_SRST_ST_DDR0_OFFSET 0

#define DVPP0_CFG_SRST_ST_HHA0_LEN    1
#define DVPP0_CFG_SRST_ST_HHA0_OFFSET 0

#define DVPP0_CFG_SRST_ST_MN0_LEN    1
#define DVPP0_CFG_SRST_ST_MN0_OFFSET 0

#define DVPP0_CFG_SRST_ST_EXMBIST0_ARESET_LEN    1
#define DVPP0_CFG_SRST_ST_EXMBIST0_ARESET_OFFSET 1
#define DVPP0_CFG_SRST_ST_EXMBIST0_LEN           1
#define DVPP0_CFG_SRST_ST_EXMBIST0_OFFSET        0

#define DVPP0_CFG_SRST_ST_DUM0_LEN      1
#define DVPP0_CFG_SRST_ST_DUM0_OFFSET   2
#define DVPP0_CFG_SRST_ST_P2P_M0_LEN    1
#define DVPP0_CFG_SRST_ST_P2P_M0_OFFSET 1

#define DVPP0_CFG_SRST_ST_L2BUFF0_LEN    1
#define DVPP0_CFG_SRST_ST_L2BUFF0_OFFSET 0

#define DVPP0_CFG_I2C0_SDA_CFG_ST_LEN        1
#define DVPP0_CFG_I2C0_SDA_CFG_ST_OFFSET     11
#define DVPP0_CFG_I2C0_DAT_OE_CFG_ST_LEN     1
#define DVPP0_CFG_I2C0_DAT_OE_CFG_ST_OFFSET  10
#define DVPP0_CFG_I2C0_DAT_MUX_SEL_ST_LEN    1
#define DVPP0_CFG_I2C0_DAT_MUX_SEL_ST_OFFSET 9
#define DVPP0_CFG_I2C0_SCL_CFG_ST_LEN        1
#define DVPP0_CFG_I2C0_SCL_CFG_ST_OFFSET     8
#define DVPP0_CFG_I2C0_CLK_OE_CFG_ST_LEN     1
#define DVPP0_CFG_I2C0_CLK_OE_CFG_ST_OFFSET  7
#define DVPP0_CFG_I2C0_CLK_MUX_SEL_ST_LEN    1
#define DVPP0_CFG_I2C0_CLK_MUX_SEL_ST_OFFSET 6
#define DVPP0_CFG_I2C1_SDA_CFG_ST_LEN        1
#define DVPP0_CFG_I2C1_SDA_CFG_ST_OFFSET     5
#define DVPP0_CFG_I2C1_DAT_OE_CFG_ST_LEN     1
#define DVPP0_CFG_I2C1_DAT_OE_CFG_ST_OFFSET  4
#define DVPP0_CFG_I2C1_DAT_MUX_SEL_ST_LEN    1
#define DVPP0_CFG_I2C1_DAT_MUX_SEL_ST_OFFSET 3
#define DVPP0_CFG_I2C1_SCL_CFG_ST_LEN        1
#define DVPP0_CFG_I2C1_SCL_CFG_ST_OFFSET     2
#define DVPP0_CFG_I2C1_CLK_OE_CFG_ST_LEN     1
#define DVPP0_CFG_I2C1_CLK_OE_CFG_ST_OFFSET  1
#define DVPP0_CFG_I2C1_CLK_MUX_SEL_ST_LEN    1
#define DVPP0_CFG_I2C1_CLK_MUX_SEL_ST_OFFSET 0

#define DVPP0_CFG_SC_DEBUG_INFO_LEN    32
#define DVPP0_CFG_SC_DEBUG_INFO_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VDEC0_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VDEC0_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VDEC0_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VDEC0_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VDEC0_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VDEC1_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VDEC1_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VDEC1_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VDEC1_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VDEC1_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC0_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC0_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC0_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC0_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC0_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC0_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC0_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC0_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC1_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC1_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC1_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC1_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC1_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC1_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC1_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC1_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC2_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC2_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC2_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC2_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC2_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC2_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC2_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC2_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC3_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC3_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC3_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC3_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VPC3_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VPC3_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VPC3_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VPC3_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_JPEG_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_JPEG_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_JPEG_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_JPEG_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_JPEG_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_JPEG_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_JPEG_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_JPEG_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VENC_AR_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VENC_AR_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VENC_AR_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VENC_AR_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_SC_VENC_AW_DEBUG_INFO_31_0_LEN    32
#define DVPP0_CFG_SC_VENC_AW_DEBUG_INFO_31_0_OFFSET 0

#define DVPP0_CFG_SC_VENC_AW_DEBUG_INFO_63_32_LEN    32
#define DVPP0_CFG_SC_VENC_AW_DEBUG_INFO_63_32_OFFSET 0

#define DVPP0_CFG_UCE_PROG_STATE_DDRC3_LEN    8
#define DVPP0_CFG_UCE_PROG_STATE_DDRC3_OFFSET 24
#define DVPP0_CFG_UCE_PROG_STATE_DDRC2_LEN    8
#define DVPP0_CFG_UCE_PROG_STATE_DDRC2_OFFSET 16
#define DVPP0_CFG_UCE_PROG_STATE_DDRC1_LEN    8
#define DVPP0_CFG_UCE_PROG_STATE_DDRC1_OFFSET 8
#define DVPP0_CFG_UCE_PROG_STATE_DDRC0_LEN    8
#define DVPP0_CFG_UCE_PROG_STATE_DDRC0_OFFSET 0

#define DVPP0_CFG_EFUSE_VDEC_SPEC_HALF_LEN    1
#define DVPP0_CFG_EFUSE_VDEC_SPEC_HALF_OFFSET 0

#define DVPP0_CFG_DVPP_CFG_VERSION_LEN    32
#define DVPP0_CFG_DVPP_CFG_VERSION_OFFSET 0

#define DVPP0_CFG_DVPP_CFG_MAGIC_WORD_LEN    32
#define DVPP0_CFG_DVPP_CFG_MAGIC_WORD_OFFSET 0

#define DVPP0_CFG_SYSCTRL_LOCK_LEN    32
#define DVPP0_CFG_SYSCTRL_LOCK_OFFSET 0

#define DVPP0_CFG_SYSCTRL_UNLOCK_LEN    32
#define DVPP0_CFG_SYSCTRL_UNLOCK_OFFSET 0

#define DVPP0_CFG_ECO_RSV0_LEN    32
#define DVPP0_CFG_ECO_RSV0_OFFSET 0

#define DVPP0_CFG_ECO_RSV1_LEN    32
#define DVPP0_CFG_ECO_RSV1_OFFSET 0

#define DVPP0_CFG_ECO_RSV2_LEN    32
#define DVPP0_CFG_ECO_RSV2_OFFSET 0

#define DVPP0_CFG_ECO_RSV3_LEN    32
#define DVPP0_CFG_ECO_RSV3_OFFSET 0

#define DVPP0_CFG_PROTOTYPE_CLK_LEN    32
#define DVPP0_CFG_PROTOTYPE_CLK_OFFSET 0

#define DVPP0_CFG_PROTOTYPE_RST_N_LEN    32
#define DVPP0_CFG_PROTOTYPE_RST_N_OFFSET 0

#endif // __DVPP0_CFG_REG_OFFSET_FIELD_H__
